Detector 4

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This page contains information about changes/issues for RHESSI detector 4 after the 2014 anneal.  Detector updates from 2012-mid 2014 can be found here: [[Detector 4 anneal 2012]]
This page contains information about changes/issues for RHESSI detector 4 after the 2014 anneal.  Detector updates from 2012-mid 2014 can be found here: [[Detector 4 anneal 2012]]
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===Notes===
+
=== Post 2014 Anneal ===
After the 2014 anneal, detector 4 is UNSEGMENTED.
After the 2014 anneal, detector 4 is UNSEGMENTED.
Line 126: Line 126:
  2016-008-01:35:37 /ITMOFF VALUE=DIB4 ; turn off G4 events
  2016-008-01:35:37 /ITMOFF VALUE=DIB4 ; turn off G4 events
  2016-008-01:35:46 /IHVDAC DETECTOR=4, VOLTAGE=28 ; return to 500 V
  2016-008-01:35:46 /IHVDAC DETECTOR=4, VOLTAGE=28 ; return to 500 V
 +
 +
* 2016 January 13: A experiment was performed consisting in lowering the voltage of the detector from 500V to 200V, start taking events
 +
 +
2016-013-21:21:18 /IHVDAC DETECTOR=4, VOLTAGE=11 ; 200 V
 +
2016-013-21:21:41 G4 events on
 +
2016-013-21:24:39 G4 events off
 +
 +
2016-013-23:00:55 G4 events on
 +
2016-013-23:08:06 G4 events off
 +
 +
* On January 27 the slow front the threshold was changed to A0 to evaluate the impact of such change on the SSR fill level. The threshold change was made for the duration of the pass, returning to the original value of C0. The result of this experiment demonstrated a minimal impact on the SSR fill level.
 +
 +
2016-027-20:13:52 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
 +
2016-027-20:14:00 /IDPLOAD VALUE=0xA0  ; was 0xC0
 +
 +
2016-027-20:19:10 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
 +
2016-027-20:19:18 /IDPLOAD VALUE=0xC0  ; was 0xA0
 +
 +
* On January 29, we changed the detector slow front threshold to A0 for one orbit and egain evaluated the impact of this change on the SSR fill level. Again the impact was minimal. At the end of the orbit the slow front threshold was changed to C0.
 +
 +
2016-029-17:44:48 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
 +
2016-029-17:45:10 /IDPLOAD VALUE=0xA0  ; was 0xC0
 +
 +
16-029-19:26:50 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
 +
16-029-19:27:07 /IDPLOAD VALUE=0xC0  ; was 0xA0
 +
 +
At 22:43:12 UT on January 29 the slow front threshold was changed to A0. Since then no detrimental repercussions on the SSR fill level have been observed.
 +
 +
16-029-22:43:12 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
 +
16-029-22:43:22 /IDPLOAD VALUE=0xA0  ; was 0xC0
 +
 +
=== Post 2016 Anneal ===
 +
 +
* 2016 April 27 (DOY 118):  Started turning on D4. HV reached 3995 V by April 29, ~03:40
 +
 +
16-119-00:49:49 start ihv_ramp_stage1_g1_g4_g7 (HV = 0x0A, ~200 V)
 +
16-119-02:27:48 start ihv_ramp_stage2_g1_g4_g7 (HV = 0x33, 980 V)
 +
16-119-04:08:00 start ihv_ramp_stage3_g1_g4_g7 (HV = 0x67, 1985 V)
 +
16-120-00:22:16 start ihv_ramp_stage4_g1_g4_g7 (HV = 0x9A, ~3000 V)
 +
16-120-02:01:36 start ihv_ramp_stage5_g1_g4_g7 (HV = 0xB3, ~3500 V)
 +
16-120-03:41:12 start ihv_ramp_stage6_g1_g4_g7 (HV = 0xCE, 3995 V)
 +
 +
* 2016 April 29, Front fast and front-slow thresholds were raised to 0x38 and 0x30, respectively.
 +
 +
16-120-00:28:14 /IDPUTABLE4 OFFSET=FRONTFASTDAC
 +
16-120-00:28:25 /IDPLOAD VALUE=0x30
 +
 +
16-120-22:21:52  /IDPUTABLE4 OFFSET=FRONTFASTDAC
 +
16-120-22:22:19  /IDPLOAD VALUE=0x40  ; was 0x30
 +
 +
16-120-23:58:19 /IDPUTABLE4 OFFSET=FRONTFASTDAC
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16-120-23:58:36 /IDPLOAD VALUE=0x38
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 +
16-120-03:45:16 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
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16-120-03:45:31 /IDPLOAD VALUE=0x30
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 +
* May 18, 2016 This detector turned off
 +
2016-139-18:52:03 /ihvdac detector=4, voltage=0
 +
2016-139-18:56:31 /idibpwroff value=4
===D4 front slow LLD threshold history===
===D4 front slow LLD threshold history===
Line 151: Line 210:
|-
|-
| 2015 Oct 05 00:39:19 UTC || 0xFF (was 0xF0)
| 2015 Oct 05 00:39:19 UTC || 0xFF (was 0xF0)
 +
|-
 +
| 2016 Jan 27 20:14:00 UTC || 0xA0 (was 0xC0)
 +
|-
 +
| 2016 Jan 27 20:19:18 UTC || 0xC0 (was 0xA0)
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|-
 +
| 2016 Jan 29 17:45:10 UTC || 0xA0 (was 0xC0)
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|-
 +
| 2016 Jan 29 19:27:07 UTC || 0xC0 (was 0xA0)
 +
|-
 +
| 2016 Jan 29 22:43:22 UTC || 0xA0 (was 0xC0)
 +
|-
 +
| post 2016 anneal || 0x30
|-
|-
|}
|}
 +
===D4 front fast LLD threshold history===
===D4 front fast LLD threshold history===
Line 180: Line 252:
|-
|-
| 2015-Sep-09 17:50:35 UTC || 0xFF (was 0xF0)
| 2015-Sep-09 17:50:35 UTC || 0xFF (was 0xF0)
 +
|-
 +
| post 2016 anneal || 0x38
|-
|-
|}
|}
 +
===D4 rear slow LLD threshold history===
===D4 rear slow LLD threshold history===
Line 213: Line 288:
| 2015-Dec-10 21:37:30 UTC || 1000 V (was 1519 V)
| 2015-Dec-10 21:37:30 UTC || 1000 V (was 1519 V)
|-
|-
-
| 2015-12-17  18:47:12 UTC ||  500 V
+
| 2015-12-17  18:47:12 UTC ||  500 V (was 1000 V)
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|-
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| 2016-01-08  01:31:37 UTC ||  200 V (was 500 V)
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|-
 +
| 2016-01-08  01:35:37 UTC ||  500 V (was 200 V)
 +
|-
 +
| 2016-01-13 21:21:18 UTC ||  200 V (was 500 V)
 +
|-
 +
| post 2016 anneal || 3995 V
 +
|-
 +
| 2016-05-18 18:56:31 || 0V
|}
|}

Latest revision as of 15:24, 4 November 2016

This page contains information about changes/issues for RHESSI detector 4 after the 2014 anneal. Detector updates from 2012-mid 2014 can be found here: Detector 4 anneal 2012

Contents

Post 2014 Anneal

After the 2014 anneal, detector 4 is UNSEGMENTED.

15-141-19:24:10 start idib_chg_thrshld (4, FRONT, SLOW, 0x68)  --> Was 0x60
15-141-19:24:22 /IDPUDUMPTABL TABLE=DIBTBL4
15-141-19:24:22 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-141-19:24:31 /IDPLOAD VALUE=0x68
2015-152-17:00:18 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-152-17:00:31 /IDPLOAD VALUE=0x60  ; was 0x50
2015-188-18:48:17 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-188-18:48:34 /IDPLOAD VALUE=0x70  ; was 0x60
2015-191-19:21:17 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-191-19:21:25 /IDPLOAD VALUE=0x80  ; was 0x70
2015-205-17:22:21 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-205-17:22:30 /IDPLOAD VALUE=0x90  ; was 0x80
 2015-225-16:45:08 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
 2015-225-16:45:20 /IDPLOAD VALUE=0x80  ; was 0x70
15-232-22:17:53 start idib_chg_thrshld (4, FRONT, FAST, 0xA0)
15-232-22:18:12 /IDPUDUMPTABL TABLE=DIBTBL4
15-232-22:18:12 /IDPUTABLE4 OFFSET=FRONTFASTDAC
15-232-22:18:25 /IDPLOAD VALUE=0xA0
15-232-22:19:13 start idib_chg_thrshld (4, FRONT, FAST, 0xB0)
15-232-22:19:23 /IDPUDUMPTABL TABLE=DIBTBL4
15-232-22:19:23 /IDPUTABLE4 OFFSET=FRONTFASTDAC
15-232-22:19:32 /IDPLOAD VALUE=0xB0
2015-236-20:44:08 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-236-20:44:22 /IDPLOAD VALUE=0xD0  ; was 0xB0
2015-237-00:02:14 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-237-00:02:22 /IDPLOAD VALUE=0xE0 ;  was 0xD0
2015-239-17:55:53 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-17:56:02 /IDPLOAD VALUE=0x90  ; was 0x80
2015-239-17:56:56 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-17:57:05 /IDPLOAD VALUE=0xA0  ; was 0x90
2015-239-19:34:23 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-19:34:32 /IDPLOAD VALUE=0xC0  ; was 0xA0
2015-239-19:37:01 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-239-19:37:09 /IDPLOAD VALUE=0xF0  ; was 0xE0
2015-239-19:39:38 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-19:39:47 /IDPLOAD VALUE=0xC3  ; was 0xC0
2015-239-21:14:24 /ihvdac detector=4, voltage=226
2015-239-21:15:53 /ihvdac detector=4, voltage=221
2015-252-17:50:20 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-252-17:50:35 /IDPLOAD VALUE=0xFF  ; was 0xF0
2015-252-17:49:33 /IHVDAC DETECTOR=4, VOLTAGE=200 (3898 V)
2015-257-17:36:45 /IHVDAC DETECTOR=4, voltage=185 (3602 V, was 3897 V)
2015-266-19:25:51 /IHVDAC DETECTOR=4, VOLTAGE=134 (2598 V)


15-279-00:37:28 start idib_chg_thrshld (4, FRONT, SLOW, 0xE0)  ; was 0xD0
15-279-00:37:32 /IDPUDUMPTABL TABLE=DIBTBL4
15-279-00:37:32 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-279-00:37:42 /IDPLOAD VALUE=0xE0
15-279-00:38:20 start idib_chg_thrshld (4, FRONT, SLOW, 0xF0)  ; was 0xE0
15-279-00:38:24 /IDPUDUMPTABL TABLE=DIBTBL4
15-279-00:38:24 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-279-00:38:29 /IDPLOAD VALUE=0xF0
15-279-00:39:19 start idib_chg_thrshld (4, FRONT, SLOW, 0xFF)  ; was 0xF0
15-279-00:39:23 /IDPUDUMPTABL TABLE=DIBTBL4
15-279-00:39:23 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-279-00:39:30 /IDPLOAD VALUE=0xFF

In order to deal with the high SSR fill level we halted collection of detector 4 events. We also loaded a modified version of RTS 26 so that G4 events would stay off, when the other detector events were turned back on, after each eclipse exit. We noted an immediate decrease in the SSR write rate, as soon as G4 events were turned off. This SSR fill level has since begun to decrease.

Turn off G4 events
15-279-02:16:10 /itmoff value=dib4

Load modified RTS 26 so the G4 events stay off

15-279-02:17:05 start sc_tbl_loadpkt("T15271SLTN61_No_G4_G9.00")
2015-344-21:37:30 /ihvdac detector=4, voltage=53 ; was ~1519V
from 346-00:32:44 to 346-00:36:16 UTC (day 346 = December 12).
2016-008-01:31:37 /IHVDAC DETECTOR=4, VOLTAGE=10 ; 200 V
2016-008-01:32:07 /ITMON VALUE=AFE3 ; turn on G4 events
2016-008-01:35:37 /ITMOFF VALUE=DIB4 ; turn off G4 events
2016-008-01:35:46 /IHVDAC DETECTOR=4, VOLTAGE=28 ; return to 500 V
2016-013-21:21:18 /IHVDAC DETECTOR=4, VOLTAGE=11 ; 200 V
2016-013-21:21:41 G4 events on
2016-013-21:24:39 G4 events off
2016-013-23:00:55 G4 events on
2016-013-23:08:06 G4 events off
2016-027-20:13:52 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2016-027-20:14:00 /IDPLOAD VALUE=0xA0  ; was 0xC0
2016-027-20:19:10 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2016-027-20:19:18 /IDPLOAD VALUE=0xC0  ; was 0xA0
2016-029-17:44:48 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2016-029-17:45:10 /IDPLOAD VALUE=0xA0  ; was 0xC0
16-029-19:26:50 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
16-029-19:27:07 /IDPLOAD VALUE=0xC0  ; was 0xA0

At 22:43:12 UT on January 29 the slow front threshold was changed to A0. Since then no detrimental repercussions on the SSR fill level have been observed.

16-029-22:43:12 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
16-029-22:43:22 /IDPLOAD VALUE=0xA0  ; was 0xC0

Post 2016 Anneal

16-119-00:49:49 start ihv_ramp_stage1_g1_g4_g7 (HV = 0x0A, ~200 V)
16-119-02:27:48 start ihv_ramp_stage2_g1_g4_g7 (HV = 0x33, 980 V)
16-119-04:08:00 start ihv_ramp_stage3_g1_g4_g7 (HV = 0x67, 1985 V)
16-120-00:22:16 start ihv_ramp_stage4_g1_g4_g7 (HV = 0x9A, ~3000 V)
16-120-02:01:36 start ihv_ramp_stage5_g1_g4_g7 (HV = 0xB3, ~3500 V)
16-120-03:41:12 start ihv_ramp_stage6_g1_g4_g7 (HV = 0xCE, 3995 V)
16-120-00:28:14 /IDPUTABLE4 OFFSET=FRONTFASTDAC
16-120-00:28:25 /IDPLOAD VALUE=0x30

16-120-22:21:52  /IDPUTABLE4 OFFSET=FRONTFASTDAC
16-120-22:22:19  /IDPLOAD VALUE=0x40  ; was 0x30

16-120-23:58:19 /IDPUTABLE4 OFFSET=FRONTFASTDAC
16-120-23:58:36 /IDPLOAD VALUE=0x38

16-120-03:45:16 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
16-120-03:45:31 /IDPLOAD VALUE=0x30
2016-139-18:52:03 /ihvdac detector=4, voltage=0
2016-139-18:56:31 /idibpwroff value=4

D4 front slow LLD threshold history

post 2014 anneal 0x50
2015 May 21 19:24 UTC 0x70 (was 0x60)
2015 Aug 13 16:45 UTC 0x80 (was 0x70)
2015 Aug 27 17:56:02 UTC 0x90 (was 0x80)
2015 Aug 27 17:57:05 UTC 0xA0 (was 0x90)
2015 Aug 27 19:34:32 UTC 0xC0 (was 0xA0)
2015 Aug 27 19:39:47 UTC 0xC3 (was 0xC0)
2015 Sep 17 06:35:40 UTC 0xD0 (was 0xC3)
2015 Oct 05 00:37:28 UTC 0xE0 (was 0xD0)
2015 Oct 05 00:38:20 UTC 0xF0 (was 0xE0)
2015 Oct 05 00:39:19 UTC 0xFF (was 0xF0)
2016 Jan 27 20:14:00 UTC 0xA0 (was 0xC0)
2016 Jan 27 20:19:18 UTC 0xC0 (was 0xA0)
2016 Jan 29 17:45:10 UTC 0xA0 (was 0xC0)
2016 Jan 29 19:27:07 UTC 0xC0 (was 0xA0)
2016 Jan 29 22:43:22 UTC 0xA0 (was 0xC0)
post 2016 anneal 0x30


D4 front fast LLD threshold history

post 2014 anneal 0x30
2014-Dec-8 after 22:05 UTC 0x50 (was 0x30)
2015-Jun-02 17:00:31 UTC 0x60 (was 0x50)
2015-Jul-07 18:48:34 UTC 0x70 (was 0x60)
2015-Jul-07 19:21:25 UTC 0x80 (was 0x70)
2015-Jul-24 17:22:30 UTC 0x90 (was 0x80)
2015-Aug-20 22:18:25 UTC 0xA0 (was 0x90)
2015-Aug-20 22:19:32 UTC 0xB0 (was 0xA0)
2015-Aug-24 20:44:22 UTC 0xD0 (was 0xB0)
2015-Aug-25 00:02:22 UTC 0xE0 (was 0xD0)
2015-Aug-27 19:37:09 UTC 0xF0 (was 0xE0)
2015-Sep-09 17:50:35 UTC 0xFF (was 0xF0)
post 2016 anneal 0x38


D4 rear slow LLD threshold history

post 2014 anneal 0x30

D4 rear fast LLD threshold history

post 2014 anneal 0x45
2015-Sep-17 06:37:27UTC 0x55 (was 0x45)

D4 HV history

post 2014 anneal 4510 V
2015-Aug-27 21:15:53 UTC 4289 V (was 4510 V)
2015-Sep-09 17:49:33 UTC 3898 V (was 4289 V)
2015-Sep-14 17:36:45 UTC 3602 V (was 3897 V)
2015-Sep-23 19:25:51 UTC 2598 V (was 3602 V)
2015-Dec-10 21:37:30 UTC 1000 V (was 1519 V)
2015-12-17 18:47:12 UTC 500 V (was 1000 V)
2016-01-08 01:31:37 UTC 200 V (was 500 V)
2016-01-08 01:35:37 UTC 500 V (was 200 V)
2016-01-13 21:21:18 UTC 200 V (was 500 V)
post 2016 anneal 3995 V
2016-05-18 18:56:31 0V
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