Detector 4

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Revision as of 22:26, 30 September 2015 (view source) Lglesener (Talk | contribs) ← Older edit		Revision as of 22:32, 7 October 2015 (view source) Hazelbain (Talk | contribs) (→Notes) Newer edit →
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	2015-266-19:25:51 /IHVDAC DETECTOR=4, VOLTAGE=134 (2598 V)		2015-266-19:25:51 /IHVDAC DETECTOR=4, VOLTAGE=134 (2598 V)
		+
		+	* 5th October 2015: G4 was primarily responsible was the increasing SSR fill level (max ~68%). Over the weekend the behavior of D4 changed causing very high fast valids and live time at or near 0%.  This low live time has prevented G4 from putting a lot of noise into the SSR. However over the previous few days, the fast valids declined and the livetime rose to around 74%.  This has allowed G4 to begin putting more than 9k events per second.  Because of this, we further increased the G4 front slow valid, in steps up to max threshold 0xFF.  This had no effect whatsoever (slow valid counts appear to be stuck on just one value).  This is similar to some of the strange behavior was previously saw in G9.
		+
		+	15-279-00:37:28 start idib_chg_thrshld (4, FRONT, SLOW, 0xE0)  ; was 0xD0
		+	15-279-00:37:32 /IDPUDUMPTABL TABLE=DIBTBL4
		+	15-279-00:37:32 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
		+	15-279-00:37:42 /IDPLOAD VALUE=0xE0
		+
		+	15-279-00:38:20 start idib_chg_thrshld (4, FRONT, SLOW, 0xF0)  ; was 0xE0
		+	15-279-00:38:24 /IDPUDUMPTABL TABLE=DIBTBL4
		+	15-279-00:38:24 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
		+	15-279-00:38:29 /IDPLOAD VALUE=0xF0
		+
		+	15-279-00:39:19 start idib_chg_thrshld (4, FRONT, SLOW, 0xFF)  ; was 0xF0
		+	15-279-00:39:23 /IDPUDUMPTABL TABLE=DIBTBL4
		+	15-279-00:39:23 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
		+	15-279-00:39:30 /IDPLOAD VALUE=0xFF
		+
		+	In order to deal with the high SSR fill level we halted collection of detector 4 events.  We also loaded a modified version of RTS 26 so that G4 events would stay off, when the other detector events were turned back on, after each eclipse exit.  We noted an immediate decrease in the SSR write rate, as soon as G4 events were turned off.  This SSR fill level has since begun to decrease.
		+
		+	Turn off G4 events
		+	15-279-02:16:10 /itmoff value=dib4
		+
		+	Load modified RTS 26 so the G4 events stay off
		+	15-279-02:17:05 start sc_tbl_loadpkt("T15271SLTN61_No_G4_G9.00")
	===D4 front slow LLD threshold history===		===D4 front slow LLD threshold history===

---

Revision as of 22:32, 7 October 2015

This page contains information about changes/issues for RHESSI detector 4 after the 2014 anneal. Detector updates from 2012-mid 2014 can be found here: Detector 4 anneal 2012

Contents 1 Notes 2 D4 front slow LLD threshold history 3 D4 front fast LLD threshold history 4 D4 rear slow LLD threshold history 5 D4 rear fast LLD threshold history 6 D4 HV history

Notes

After the 2014 anneal, detector 4 is UNSEGMENTED.

• On May 21 starting at 19:24 UTC we raised up the Slow threshold for the Front segment.

15-141-19:24:10 start idib_chg_thrshld (4, FRONT, SLOW, 0x68)  --> Was 0x60
15-141-19:24:22 /IDPUDUMPTABL TABLE=DIBTBL4
15-141-19:24:22 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-141-19:24:31 /IDPLOAD VALUE=0x68

• Raised front fast threshold due to elevated counts. This change reduced counts and increased livetime

2015-152-17:00:18 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-152-17:00:31 /IDPLOAD VALUE=0x60  ; was 0x50

• On 2015 July 7, D4 front fast threshold was raised due to decreased livetime.

2015-188-18:48:17 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-188-18:48:34 /IDPLOAD VALUE=0x70  ; was 0x60

• The front fast threshold was increased on July 10 2015 due to low livetime due to high fast rates. This action was effective in raising the livetime.

2015-191-19:21:17 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-191-19:21:25 /IDPLOAD VALUE=0x80  ; was 0x70

• The front fast threshold was increased on July 24 2015 due to low livetime due to high fast rates. This action was effective in raising the livetime, to ~90%.

2015-205-17:22:21 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-205-17:22:30 /IDPLOAD VALUE=0x90  ; was 0x80

• 2015-08-13: Front slow valid threshold was raised by 10 steps; trying to get the slow valid rates down.

 2015-225-16:45:08 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
 2015-225-16:45:20 /IDPLOAD VALUE=0x80  ; was 0x70

• On Aug 20, 2015 the front fast threshold was raised, in two commands of 16 steps each, in order to lower fast rates and free up livetime. This was successful but probably needs to be repeated. Livetime rose from ~0% to ~50%. The D4 threshold should be raised again to further raise the livetime.

15-232-22:17:53 start idib_chg_thrshld (4, FRONT, FAST, 0xA0)
15-232-22:18:12 /IDPUDUMPTABL TABLE=DIBTBL4
15-232-22:18:12 /IDPUTABLE4 OFFSET=FRONTFASTDAC
15-232-22:18:25 /IDPLOAD VALUE=0xA0

15-232-22:19:13 start idib_chg_thrshld (4, FRONT, FAST, 0xB0)
15-232-22:19:23 /IDPUDUMPTABL TABLE=DIBTBL4
15-232-22:19:23 /IDPUTABLE4 OFFSET=FRONTFASTDAC
15-232-22:19:32 /IDPLOAD VALUE=0xB0

• On Aug 24, 2015 the front fast threshold was raised twice to free up livetime. This was successful. Note that these changes are working, but we're almost out of head room!

2015-236-20:44:08 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-236-20:44:22 /IDPLOAD VALUE=0xD0  ; was 0xB0

2015-237-00:02:14 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-237-00:02:22 /IDPLOAD VALUE=0xE0 ;  was 0xD0

• As was discussed during the last meeting, detector 4 showed elevated slow front rates. Following the suggestions of the previous tohban, on August 27 the slow front threshold was increased but no change was observed at all. As the front fast rates were also elevated, a change in the front fast threshold was performed. This change increased its livetimes and the slow front rates, as was expected. Then we decrease D4 HV by 200V, a very conservative value as we would like the detector to segment. However the HV change did not have any impact the front slow rates. The detector remains in the same condition with the slow front threshold at 0xC3.

2015-239-17:55:53 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-17:56:02 /IDPLOAD VALUE=0x90  ; was 0x80

2015-239-17:56:56 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-17:57:05 /IDPLOAD VALUE=0xA0  ; was 0x90

2015-239-19:34:23 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-19:34:32 /IDPLOAD VALUE=0xC0  ; was 0xA0

2015-239-19:37:01 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-239-19:37:09 /IDPLOAD VALUE=0xF0  ; was 0xE0

2015-239-19:39:38 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-19:39:47 /IDPLOAD VALUE=0xC3  ; was 0xC0

2015-239-21:14:24 /ihvdac detector=4, voltage=226
2015-239-21:15:53 /ihvdac detector=4, voltage=221

• The front fast threshold was changed on Sep 9 2015 due to low livetime. HV was lowered.

2015-252-17:50:20 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-252-17:50:35 /IDPLOAD VALUE=0xFF  ; was 0xF0
2015-252-17:49:33 /IHVDAC DETECTOR=4, VOLTAGE=200 (3898 V)

• On September 14 2015, HV was lowered again, with no long term effect.

2015-257-17:36:45 /IHVDAC DETECTOR=4, voltage=185 (3602 V, was 3897 V)

• Sept. 23 2015: Despite our best efforts, there's been no success in recovering livetime from D4. The front segment livetime is essentially 0. Since desperate times call for desperate measures, we're lowering the HV by 1000V to try and recover some performance. (This was temporarily tried last week, for an orbit, and the livetime did rise to 30%.) The detector does not seem to be anywhere near segmenting. UPDATE Sept. 24: this drop was successful in bringing the fast rates down some, from 4x10^5 to 10^5. This freed up some livetime, which is now at ~35%. However, it also allowed the slow rates to skyrocket, to about 3000. This is probably cutting into the SSR, and so now the SSR fill is gradually rising (13% min today vs ~4% min yesterday). Action MAY need to be taken to reduce the fill rate.

2015-266-19:25:51 /IHVDAC DETECTOR=4, VOLTAGE=134 (2598 V)

• 5th October 2015: G4 was primarily responsible was the increasing SSR fill level (max ~68%). Over the weekend the behavior of D4 changed causing very high fast valids and live time at or near 0%. This low live time has prevented G4 from putting a lot of noise into the SSR. However over the previous few days, the fast valids declined and the livetime rose to around 74%. This has allowed G4 to begin putting more than 9k events per second. Because of this, we further increased the G4 front slow valid, in steps up to max threshold 0xFF. This had no effect whatsoever (slow valid counts appear to be stuck on just one value). This is similar to some of the strange behavior was previously saw in G9.

15-279-00:37:28 start idib_chg_thrshld (4, FRONT, SLOW, 0xE0)  ; was 0xD0
15-279-00:37:32 /IDPUDUMPTABL TABLE=DIBTBL4
15-279-00:37:32 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-279-00:37:42 /IDPLOAD VALUE=0xE0

15-279-00:38:20 start idib_chg_thrshld (4, FRONT, SLOW, 0xF0)  ; was 0xE0
15-279-00:38:24 /IDPUDUMPTABL TABLE=DIBTBL4
15-279-00:38:24 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-279-00:38:29 /IDPLOAD VALUE=0xF0

15-279-00:39:19 start idib_chg_thrshld (4, FRONT, SLOW, 0xFF)  ; was 0xF0
15-279-00:39:23 /IDPUDUMPTABL TABLE=DIBTBL4
15-279-00:39:23 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-279-00:39:30 /IDPLOAD VALUE=0xFF

In order to deal with the high SSR fill level we halted collection of detector 4 events. We also loaded a modified version of RTS 26 so that G4 events would stay off, when the other detector events were turned back on, after each eclipse exit. We noted an immediate decrease in the SSR write rate, as soon as G4 events were turned off. This SSR fill level has since begun to decrease.

Turn off G4 events

15-279-02:16:10 /itmoff value=dib4

Load modified RTS 26 so the G4 events stay off

15-279-02:17:05 start sc_tbl_loadpkt("T15271SLTN61_No_G4_G9.00")

D4 front slow LLD threshold history

post 2014 anneal	0x50
2015 May 21 19:24 UTC	0x70 (was 0x60)
2015 Aug 13 16:45 UTC	0x80 (was 0x70)
2015 Aug 27 17:56:02 UTC	0x90 (was 0x80)
2015 Aug 27 17:57:05 UTC	0xA0 (was 0x90)
2015 Aug 27 19:34:32 UTC	0xC0 (was 0xA0)
2015 Aug 27 19:39:47 UTC	0xC3 (was 0xC0)
2015 Sep 17 06:35:40 UTC	0xD0 (was 0xC3)

D4 front fast LLD threshold history

post 2014 anneal	0x30
2014-Dec-8 after 22:05 UTC	0x50 (was 0x30)
2015-Jun-02 17:00:31 UTC	0x60 (was 0x50)
2015-Jul-07 18:48:34 UTC	0x70 (was 0x60)
2015-Jul-07 19:21:25 UTC	0x80 (was 0x70)
2015-Jul-24 17:22:30 UTC	0x90 (was 0x80)
2015-Aug-20 22:18:25 UTC	0xA0 (was 0x90)
2015-Aug-20 22:19:32 UTC	0xB0 (was 0xA0)
2015-Aug-24 20:44:22 UTC	0xD0 (was 0xB0)
2015-Aug-25 00:02:22 UTC	0xE0 (was 0xD0)
2015-Aug-27 19:37:09 UTC	0xF0 (was 0xE0)
2015-Sep-09 17:50:35 UTC	0xFF (was 0xF0)

D4 rear slow LLD threshold history

post 2014 anneal

0x30

D4 rear fast LLD threshold history

post 2014 anneal	0x45
2015-Sep-17 06:37:27UTC	0x55 (was 0x45)

D4 HV history

post 2014 anneal	4510 V
2015-Aug-27 21:15:53 UTC	4289 V (was 4510 V)
2015-Sep-09 17:49:33 UTC	3898 V (was 4289 V)
2015-Sep-14 17:36:45 UTC	3602 V (was 3897 V)
2015-Sep-23 19:25:51 UTC	2598 V (was 3602 V)