Detector 4

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This page contains information about changes/issues for RHESSI detector 4 after the 2014 anneal. Detector updates from 2012-mid 2014 can be found here: Detector 4 anneal 2012

Contents

Notes

After the 2014 anneal, detector 4 is UNSEGMENTED.

15-141-19:24:10 start idib_chg_thrshld (4, FRONT, SLOW, 0x68)  --> Was 0x60
15-141-19:24:22 /IDPUDUMPTABL TABLE=DIBTBL4
15-141-19:24:22 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-141-19:24:31 /IDPLOAD VALUE=0x68
2015-152-17:00:18 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-152-17:00:31 /IDPLOAD VALUE=0x60  ; was 0x50
2015-188-18:48:17 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-188-18:48:34 /IDPLOAD VALUE=0x70  ; was 0x60
2015-191-19:21:17 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-191-19:21:25 /IDPLOAD VALUE=0x80  ; was 0x70
2015-205-17:22:21 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-205-17:22:30 /IDPLOAD VALUE=0x90  ; was 0x80
 2015-225-16:45:08 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
 2015-225-16:45:20 /IDPLOAD VALUE=0x80  ; was 0x70
15-232-22:17:53 start idib_chg_thrshld (4, FRONT, FAST, 0xA0)
15-232-22:18:12 /IDPUDUMPTABL TABLE=DIBTBL4
15-232-22:18:12 /IDPUTABLE4 OFFSET=FRONTFASTDAC
15-232-22:18:25 /IDPLOAD VALUE=0xA0
15-232-22:19:13 start idib_chg_thrshld (4, FRONT, FAST, 0xB0)
15-232-22:19:23 /IDPUDUMPTABL TABLE=DIBTBL4
15-232-22:19:23 /IDPUTABLE4 OFFSET=FRONTFASTDAC
15-232-22:19:32 /IDPLOAD VALUE=0xB0
2015-236-20:44:08 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-236-20:44:22 /IDPLOAD VALUE=0xD0  ; was 0xB0
2015-237-00:02:14 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-237-00:02:22 /IDPLOAD VALUE=0xE0 ;  was 0xD0
2015-239-17:55:53 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-17:56:02 /IDPLOAD VALUE=0x90  ; was 0x80
2015-239-17:56:56 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-17:57:05 /IDPLOAD VALUE=0xA0  ; was 0x90
2015-239-19:34:23 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-19:34:32 /IDPLOAD VALUE=0xC0  ; was 0xA0
2015-239-19:37:01 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-239-19:37:09 /IDPLOAD VALUE=0xF0  ; was 0xE0
2015-239-19:39:38 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
2015-239-19:39:47 /IDPLOAD VALUE=0xC3  ; was 0xC0
2015-239-21:14:24 /ihvdac detector=4, voltage=226
2015-239-21:15:53 /ihvdac detector=4, voltage=221
2015-252-17:50:20 /IDPUTABLE4 OFFSET=FRONTFASTDAC
2015-252-17:50:35 /IDPLOAD VALUE=0xFF  ; was 0xF0
2015-252-17:49:33 /IHVDAC DETECTOR=4, VOLTAGE=200 (3898 V)
2015-257-17:36:45 /IHVDAC DETECTOR=4, voltage=185 (3602 V, was 3897 V)
2015-266-19:25:51 /IHVDAC DETECTOR=4, VOLTAGE=134 (2598 V)


15-279-00:37:28 start idib_chg_thrshld (4, FRONT, SLOW, 0xE0)  ; was 0xD0
15-279-00:37:32 /IDPUDUMPTABL TABLE=DIBTBL4
15-279-00:37:32 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-279-00:37:42 /IDPLOAD VALUE=0xE0
15-279-00:38:20 start idib_chg_thrshld (4, FRONT, SLOW, 0xF0)  ; was 0xE0
15-279-00:38:24 /IDPUDUMPTABL TABLE=DIBTBL4
15-279-00:38:24 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-279-00:38:29 /IDPLOAD VALUE=0xF0
15-279-00:39:19 start idib_chg_thrshld (4, FRONT, SLOW, 0xFF)  ; was 0xF0
15-279-00:39:23 /IDPUDUMPTABL TABLE=DIBTBL4
15-279-00:39:23 /IDPUTABLE4 OFFSET=FRONTSLOWDAC
15-279-00:39:30 /IDPLOAD VALUE=0xFF

In order to deal with the high SSR fill level we halted collection of detector 4 events. We also loaded a modified version of RTS 26 so that G4 events would stay off, when the other detector events were turned back on, after each eclipse exit. We noted an immediate decrease in the SSR write rate, as soon as G4 events were turned off. This SSR fill level has since begun to decrease.

Turn off G4 events

15-279-02:16:10 /itmoff value=dib4

Load modified RTS 26 so the G4 events stay off

15-279-02:17:05 start sc_tbl_loadpkt("T15271SLTN61_No_G4_G9.00")

D4 front slow LLD threshold history

post 2014 anneal 0x50
2015 May 21 19:24 UTC 0x70 (was 0x60)
2015 Aug 13 16:45 UTC 0x80 (was 0x70)
2015 Aug 27 17:56:02 UTC 0x90 (was 0x80)
2015 Aug 27 17:57:05 UTC 0xA0 (was 0x90)
2015 Aug 27 19:34:32 UTC 0xC0 (was 0xA0)
2015 Aug 27 19:39:47 UTC 0xC3 (was 0xC0)
2015 Sep 17 06:35:40 UTC 0xD0 (was 0xC3)
2015 Oct 05 00:37:28 UTC 0xE0 (was 0xD0)
2015 Oct 05 00:38:20 UTC 0xF0 (was 0xE0)
2015 Oct 05 00:39:19 UTC 0xFF (was 0xF0)

D4 front fast LLD threshold history

post 2014 anneal 0x30
2014-Dec-8 after 22:05 UTC 0x50 (was 0x30)
2015-Jun-02 17:00:31 UTC 0x60 (was 0x50)
2015-Jul-07 18:48:34 UTC 0x70 (was 0x60)
2015-Jul-07 19:21:25 UTC 0x80 (was 0x70)
2015-Jul-24 17:22:30 UTC 0x90 (was 0x80)
2015-Aug-20 22:18:25 UTC 0xA0 (was 0x90)
2015-Aug-20 22:19:32 UTC 0xB0 (was 0xA0)
2015-Aug-24 20:44:22 UTC 0xD0 (was 0xB0)
2015-Aug-25 00:02:22 UTC 0xE0 (was 0xD0)
2015-Aug-27 19:37:09 UTC 0xF0 (was 0xE0)
2015-Sep-09 17:50:35 UTC 0xFF (was 0xF0)

D4 rear slow LLD threshold history

post 2014 anneal 0x30

D4 rear fast LLD threshold history

post 2014 anneal 0x45
2015-Sep-17 06:37:27UTC 0x55 (was 0x45)

D4 HV history

post 2014 anneal 4510 V
2015-Aug-27 21:15:53 UTC 4289 V (was 4510 V)
2015-Sep-09 17:49:33 UTC 3898 V (was 4289 V)
2015-Sep-14 17:36:45 UTC 3602 V (was 3897 V)
2015-Sep-23 19:25:51 UTC 2598 V (was 3602 V)
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