Detector 4 anneal 2012
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***2014-140-18:42:54 /IDPUTABLE4 OFFSET=REARFASTDAC | ***2014-140-18:42:54 /IDPUTABLE4 OFFSET=REARFASTDAC | ||
***2014-140-18:43:13 /IDPULOAD VALUE=0xA0 | ***2014-140-18:43:13 /IDPULOAD VALUE=0xA0 | ||
| + | |||
| + | * 2014 May 28: | ||
| + | ** rear fast threshold change 0xA0 to 0xB0 | ||
| + | ***14-148-21:42:15 /IDPUTABLE4 OFFSET=REARFASTDAC | ||
| + | ***14-148-21:42:32 /IDPULOAD VALUE=0xB0 | ||
===D4 front slow LLD threshold history=== | ===D4 front slow LLD threshold history=== | ||
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| 2014-May-20 18:42:54 UTC || 0xA0 (was 0x90) | | 2014-May-20 18:42:54 UTC || 0xA0 (was 0x90) | ||
| + | |- | ||
| + | | 2014-May-28 21:42:15 UTC || 0xB0 (was 0xA0) | ||
|} | |} | ||
Revision as of 19:42, 29 May 2014
Contents |
Notes
- Detector 4 was unsegmented after the 2012 anneal. The entire detector volume is read out through the front segment electronics, so rates look higher for G4 (and also G2) than for the other detectors. (UPDATE: segmentation occurred spontaneously in late 2012; see later entries.)
- 6 November 2012: The front fast and slow thresholds on detector 4 were optimized during 2 passes. The front slow threshold was reduced significantly, down to the nominal value used by segmented detectors, without seeing a large increase in noise. The front fast threshold was lowered a little as well, but not by nearly as much.
G4 Front Slow 0x70 to 0x0C.
G4 Front Fast 0x60 to 0x50.
- 2012-dec-12: D4 has been spontaneously segmenting and desegmenting for approximately the past 30 days, it began on day 317. The high voltage was raised by 5 steps to stabilize the segmentation, and it appears to be initially successful. Brian Dennis made some plots to show that its resolution is as good as before the anneal. He also showed that the calibration used in SSW is not up to date.
- 2012 December 19: D4 was still desegmenting during and after the SAA, so the voltage was raised by 5 steps again on Dec. 17 (DOY 352) to 4215.7 V.
- 2012 December 26: The voltage was raised again on Dec. 21 to 4313.8V. D4 is now segmenting consistently, except for a very brief interval during the SAA.
- 2013 November 9: There were some isolated spikes. No further spiking occurred in the remainder of the week. See: http://sprg.ssl.berkeley.edu/~tohban/browser/?show=grth1+qlpcr+qlpfr+qlprr+monfs+monrs&date=20131109&time=051222
- 2014 March 17: The front fast threshold was lowered to its nominal value, since the detector is segmented and behaving properly. There were a couple mistakes in sending the commands but they were immediately corrected; the full list of commands is below. End result was a drop from 0x50 to 0x22.
14-076-20:34:51 /IDPUTABLE4 FRONTFASTDAC 14-076-20:37:48 /IDPULOAD VALUE=22 (in decimal, commanded to 0x16) ;was 0x50 14-076-20:38:00 /IDPULOAD VALUE=0x22 (This was written to byte 9 (Rear slow)) ;was 0x30 14-076-20:38:07 /IDPUTABLE4 FRONTFASTDAC 14-076-20:38:12 /IDPULOAD VALUE=0x22 (correct front fast threshold change) 14-076-20:38:18 /IDPULOAD VALUE=0x30 (undoing the change to the rear slow)
- 2014 April 10: The rear fast threshold was raised to 0x60. The livetime recovered from 70 to 90%.
- 2014 April 15: The rear fast threshold was raised to 0x70. The livetime recovered from 64 to 94%.
- 2014 May 12: The rear fast threshold was raised to 0x80. The livetime recovered from 54 to 92%.
- 2014 May 17:
- G4 rear fast threshold from 0x80 to 0x90
- 14-137-04:04:30 /IDPUDUMPTABL TABLE=DIBTBL4
- 14-137-04:07:38 /IDPUTABLE4 OFFSET=REARFASTDAC
- 14-137-04:07:43 /IDPULOAD VALUE=0x90 (G4 rear fast was set properly)
- G4 rear fast threshold from 0x80 to 0x90
- 2014 May 20:
- G4 rear fast threshold from 0x90 to 0xA0
- 2014-140-18:42:54 /IDPUTABLE4 OFFSET=REARFASTDAC
- 2014-140-18:43:13 /IDPULOAD VALUE=0xA0
- G4 rear fast threshold from 0x90 to 0xA0
- 2014 May 28:
- rear fast threshold change 0xA0 to 0xB0
- 14-148-21:42:15 /IDPUTABLE4 OFFSET=REARFASTDAC
- 14-148-21:42:32 /IDPULOAD VALUE=0xB0
- rear fast threshold change 0xA0 to 0xB0
D4 front slow LLD threshold history
| post 2012 anneal | 0x70 |
| 2012-Nov-06 17:39:46 UTC | 0x35 (was 0x70) |
| 2012-Nov-06 17:41:06 UTC | 0x20 (was 0x35) |
| 2012-Nov-06 19:24:53 UTC | 0x15 (was 0x20) |
| 2012-Nov-06 19:25:49 UTC | 0x0C (was 0x15) |
D4 front fast LLD threshold history
| post 2012 anneal | 0x60 |
| 2012-Nov-06 17:43:34 UTC | 0x30 (was 0x60) |
| 2012-Nov-06 17:44:03 UTC | 0x40 (was 0x30) |
| 2012-Nov-06 17:44:57 UTC | 0x50 (was 0x40) |
| 2013-Mar-17 20:37:47 UTC | 0x16 (was 0x50) |
| 2013-Mar-17 20:38:12 UTC | 0x22 (was 0x16) |
D4 rear slow LLD threshold history
| post 2012 anneal | 0x30 |
| 2013-Mar-17 20:38:00 UTC | 0x22 (was 0x30) |
| 2013-Mar-17 20:38:18 UTC | 0x30 (was 0x22) |
D4 rear fast LLD threshold history
| post 2012 anneal | 0x45 |
| 2013-Feb-06 22:08 UTC | 0x55 (was 0x45) |
| 2014-Apr-10 18:10 UTC | 0x60 (was 0x55) |
| 2014-Apr-15 16:55 UTC | 0x70 (was 0x60) |
| 2014-May-12 19:14 UTC | 0x80 (was 0x70) |
| 2014-May-17 04:03:25 UTC | 0x90 (was 0x80) |
| 2014-May-20 18:42:54 UTC | 0xA0 (was 0x90) |
| 2014-May-28 21:42:15 UTC | 0xB0 (was 0xA0) |
